One operation frequently employed in the production of semiconductors is an etching operation. In an etching operation, one or more materials are partly or wholly removed from a partially fabricated integrated circuit. Plasma etching is often used, especially where the geometries involved are small, high aspect ratios are used, or precise pattern transfer is needed.
Typically, a plasma contains electrons, as well as positive and negative ions, and some radicals. The radicals, positive ions, and negative ions interact with a substrate to etch features, surfaces and materials on the substrate. In etching conducted with an inductively coupled plasma source, a chamber coil performs a function analogous to that of a primary coil in a transformer, while the plasma performs a function analogous to that of a secondary coil in the transformer.
With the move from planar to 3D transistor structures (e.g., FinFET gate structures for logic devices), plasma etching processes need to be increasingly precise and uniform in order to produce quality products. Examples of operations that benefit from precise etching include, but are not limited to, etching/removal processes used during formation of FinFETs (e.g., source drain recess etching, FinFET gate etching, and dummy polysilicon removal), shallow trench isolation processes, and photoresist reflow processes.
Among other factors, the plasma etch processes should have good selectivity, profile angle, Iso/Dense loading, and overall uniformity. It is beneficial for an etching process to have good selectivity between the material that is etched and the material that is retained. In the context of the FinFET gate structure, this means that there should be good selectivity of the gate being etched to other exposed components such as a silicon nitride mask. The profile angle is measured as the angle between a recently etched (roughly vertical) sidewall and a horizontal plane. In many applications, the ideal profile angle is 90 degrees, producing a vertical etched step or opening. Sometimes, the local on-wafer feature density can affect the etching process. For example, an area of the wafer where features are dense may etch somewhat differently (e.g., etch more quickly, more slowly, more isotropically, more anisotropically, etc.) as compared to an area of the wafer where features are more isolated. The differences which arise due to variations in feature density are referred to as Iso/Dense loading (I/D loading). It is beneficial to minimize these differences during fabrication. In addition to meeting these and potentially other device-specific requirements, the etching process often needs to be consistently executed over the entire face of a substrate (e.g., the etch conditions and results should be uniform from the center to the edge of a semiconductor wafer).
It has been found difficult to achieve multiple objectives such as those set forth above when etching advanced structures such as FinFET gates.